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1 Ergebnisse
1
HiPR : Fast, Incremental Custom Partial Reconfiguration ..:
, In:
Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Xiao, Yuanlong
;
DeHon, Andre
- p. 155 ff. , 2022
Link:
https://dl.acm.org/doi/10.1145/3490422.3502335
RT T1 <cTitle>Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</cTitle>: T1 <Title>HiPR : Fast, Incremental Custom Partial Reconfiguration for HLS Developers</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3502335&Exemplar=1&LAN=DE A1 Xiao, Yuanlong A1 DeHon, Andre PB ACM YR 2022 K1 compile time K1 fpga K1 high-level-synthesis K1 partial reconfiguration K1 Hardware K1 Electronic design automation K1 Methodologies for EDA K1 Software tools for EDA SP 155 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3490422.3502335 DO https://dl.acm.org/doi/10.1145/3490422.3502335 SF ELIB - SuUB Bremen
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