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Silicon validation of LUT-based logic-locked IP cores:
, In:
Proceedings of the 59th ACM/IEEE Design Automation Conference
,
Kolhe, Gaurav
;
Sheaves, Tyler
;
Gubbi, Kevin Immanuel
... - p. 1189-1194 , 2022
Link:
https://dl.acm.org/doi/10.1145/3489517.3530606
RT T1 <cTitle>Proceedings of the 59th ACM/IEEE Design Automation Conference</cTitle>: T1 <Title>Silicon validation of LUT-based logic-locked IP cores</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3530606&Exemplar=1&LAN=DE A1 Kolhe, Gaurav A1 Sheaves, Tyler A1 Gubbi, Kevin Immanuel A1 Kadale, Tejas A1 Rafatirad, Setareh A1 PD, Sai Manoj A1 Sasan, Avesta A1 Mahmoodi, Hamid A1 Homayoun, Houman PB ACM YR 2022 K1 SAT attack K1 dynamic obfuscation K1 emerging devices K1 logic locking K1 power side channel attack K1 reverse engineering K1 Hardware K1 Hardware validation K1 Security and privacy K1 Security in hardware K1 Hardware attacks and countermeasures SP 1189 OP 1194 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3489517.3530606 DO https://dl.acm.org/doi/10.1145/3489517.3530606 SF ELIB - SuUB Bremen
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