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1 Ergebnisse
1
High Speed Multi-channel Data Cache Design Based on DDR3 SD..:
, In:
Proceedings of the 2022 5th International Conference on Artificial Intelligence and Pattern Recognition
,
Yang, Xiaofeng
;
Liu, Ancheng
;
Wang, Jinjin
- p. 193-196 , 2022
Link:
https://dl.acm.org/doi/10.1145/3573942.3573972
RT T1 <cTitle>Proceedings of the 2022 5th International Conference on Artificial Intelligence and Pattern Recognition</cTitle>: T1 <Title>High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3573972&Exemplar=1&LAN=DE A1 Yang, Xiaofeng A1 Liu, Ancheng A1 Wang, Jinjin PB ACM YR 2022 K1 Cache K1 DDR3 SDRAM K1 High speed K1 Large capacity K1 Multi-channel K1 Hardware K1 Communication hardware, interfaces and storage K1 Signal processing systems K1 Digital signal processing SP 193 OP 196 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3573942.3573972 DO https://dl.acm.org/doi/10.1145/3573942.3573972 SF ELIB - SuUB Bremen
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