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CPP: A Multi-Level Circuit Partitioning Predictor for Hardw..:
, In:
Proceedings of the Great Lakes Symposium on VLSI 2023
,
Zang, Xinshi
;
Chen, Lei
;
Li, Xing
... - p. 357-361 , 2023
Link:
https://dl.acm.org/doi/10.1145/3583781.3590289
RT T1 <cTitle>Proceedings of the Great Lakes Symposium on VLSI 2023</cTitle>: T1 <Title>CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3590289&Exemplar=1&LAN=DE A1 Zang, Xinshi A1 Chen, Lei A1 Li, Xing A1 Thong, Wilson W.K. A1 Sheng, Weihua A1 Young, Evangeline F.Y. A1 Wong, Martin D.F. PB ACM YR 2023 K1 circuit verification K1 partitioning K1 synthesis K1 Hardware K1 Hardware validation K1 Functional verification K1 Simulation and emulation SP 357 OP 361 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3583781.3590289 DO https://dl.acm.org/doi/10.1145/3583781.3590289 SF ELIB - SuUB Bremen
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