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1
Accelerating RTL Simulation with Hardware-Software Co-Desig:
, In:
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture
,
Elsabbagh, Fares
;
Sheikhha, Shabnam
;
Ying, Victor A.
... - p. 153-166 , 2023
Link:
https://dl.acm.org/doi/10.1145/3613424.3614257
RT T1 <cTitle>Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture</cTitle>: T1 <Title>Accelerating RTL Simulation with Hardware-Software Co-Design</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3614257&Exemplar=1&LAN=DE A1 Elsabbagh, Fares A1 Sheikhha, Shabnam A1 Ying, Victor A. A1 Nguyen, Quan M. A1 Emer, Joel S A1 Sanchez, Daniel PB ACM YR 2023 K1 dataflow execution K1 domain-specific architectures. K1 hardware acceleration K1 register-transfer-level K1 simulation K1 speculative execution K1 Hardware K1 Electronic design automation K1 Computer systems organization K1 Architectures K1 Parallel architectures SP 153 OP 166 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3613424.3614257 DO https://dl.acm.org/doi/10.1145/3613424.3614257 SF ELIB - SuUB Bremen
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