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1 Ergebnisse
1
Improving Data Reuse in NPU On-chip Memory with Interleaved..:
, In:
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture
,
Kim, Jungwoo
;
Na, Seonjin
;
Lee, Sanghyeon
.. - p. 438-451 , 2023
Link:
https://dl.acm.org/doi/10.1145/3613424.3614299
RT T1
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture
: T1
Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
UL https://suche.suub.uni-bremen.de/peid=acm-3614299&Exemplar=1&LAN=DE A1 Kim, Jungwoo A1 Na, Seonjin A1 Lee, Sanghyeon A1 Lee, Sunho A1 Huh, Jaehyuk PB ACM YR 2023 K1 DNN training K1 accelerators K1 on-chip memory K1 scheduling K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Systolic arrays K1 Other architectures K1 Neural networks SP 438 OP 451 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3613424.3614299 DO https://dl.acm.org/doi/10.1145/3613424.3614299 SF ELIB - SuUB Bremen
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