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1 Ergebnisse
1
Power and Delay Efficient Hardware Implementation with ATPG..:
, In:
Proceedings of the 13th International Conference on Advances in Information Technology
,
Arun, Anchit
;
Chakraborty, Ananya
;
Dutta, Priyanka
... - p. 1-6 , 2023
Link:
https://dl.acm.org/doi/10.1145/3628454.3631153
RT T1 <cTitle>Proceedings of the 13th International Conference on Advances in Information Technology</cTitle>: T1 <Title>Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3631153&Exemplar=1&LAN=DE A1 Arun, Anchit A1 Chakraborty, Ananya A1 Dutta, Priyanka A1 Pal, Debajyoti A1 Nag, Tridibesh A1 De, Debasis A1 Ghosh, Sudip A1 Rahaman, Hafizur PB ACM YR 2023 K1 Automatic Test Pattern Generation (ATPG) K1 Fault coverage K1 ISCAS89 K1 Test patterns K1 Urdhva Tiryagbhyam K1 Vedic multiplier K1 Hardware K1 Integrated circuits K1 Very large scale integration design K1 Hardware test K1 Robustness K1 Logic circuits K1 Arithmetic and datapath circuits SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3628454.3631153 DO https://dl.acm.org/doi/10.1145/3628454.3631153 SF ELIB - SuUB Bremen
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