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Modeling methodology for multi-die chip design based on gem..:
, In:
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design
,
Schätzle, Fabian
;
Falquez, Carlos
;
Heinen, Stefan
... - p. 35-41 , 2024
Link:
https://dl.acm.org/doi/10.1145/3642921.3642956
RT T1 <cTitle>Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design</cTitle>: T1 <Title>Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3642956&Exemplar=1&LAN=DE A1 Schätzle, Fabian A1 Falquez, Carlos A1 Heinen, Stefan A1 Ho, Nam A1 Portero, Antoni A1 Suarez, Estela A1 Van Den Boom, Johannes A1 Van Waasen, Stefan PB ACM YR 2024 K1 Cache coherency K1 Chiplets K1 High-performance Computing K1 Multi-die chip K1 SystemC TLM K1 gem5 K1 Computing methodologies K1 Modeling and simulation K1 Hardware K1 Hardware validation K1 Model development and analysis K1 Simulation types and techniques K1 Simulation support systems K1 Modeling methodologies SP 35 OP 41 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3642921.3642956 DO https://dl.acm.org/doi/10.1145/3642921.3642956 SF ELIB - SuUB Bremen
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