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Energy Efficiency Features of the Intel Alder Lake Architec..:
, In:
Proceedings of the 15th ACM/SPEC International Conference on Performance Engineering
,
Schöne, Robert
;
Velten, Markus
;
Hackenberg, Daniel
. - p. 95-106 , 2024
Link:
https://dl.acm.org/doi/10.1145/3629526.3645040
RT T1 <cTitle>Proceedings of the 15th ACM/SPEC International Conference on Performance Engineering</cTitle>: T1 <Title>Energy Efficiency Features of the Intel Alder Lake Architecture</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3645040&Exemplar=1&LAN=DE A1 Schöne, Robert A1 Velten, Markus A1 Hackenberg, Daniel A1 Ilsche, Thomas PB ACM YR 2024 K1 dvfs K1 energy efficiency K1 idle state K1 intel K1 power management K1 rapl K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multicore architectures K1 Other architectures K1 Heterogeneous (hybrid) systems K1 Hardware K1 Power and energy K1 Power estimation and optimization K1 Platform power issues K1 Chip-level power issues SP 95 OP 106 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3629526.3645040 DO https://dl.acm.org/doi/10.1145/3629526.3645040 SF ELIB - SuUB Bremen
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