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1 Ergebnisse
1
HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilo..:
, In:
Proceedings of the 34th International Workshop on Rapid System Prototyping
,
Morgan, Fearghal
;
Byrne, John Patrick
;
Bupathi, Abishek
... - p. 1-7 , 2023
Link:
https://dl.acm.org/doi/10.1145/3625223.3649280
RT T1 <cTitle>Proceedings of the 34th International Workshop on Rapid System Prototyping</cTitle>: T1 <Title>HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3649280&Exemplar=1&LAN=DE A1 Morgan, Fearghal A1 Byrne, John Patrick A1 Bupathi, Abishek A1 George, Roshan A1 Elahi, Adnan A1 Callaly, Frank A1 Kelly, Seán A1 O'Loughlin, Declan PB ACM YR 2023 K1 digital systems design K1 HDLGen-ChatGPT K1 LLM K1 ChatGPT K1 generative AI K1 design capture K1 automation K1 HDL K1 EDA K1 FPGA K1 testbench K1 VHDL K1 verilog K1 Hardware K1 Electronic design automation K1 Methodologies for EDA K1 Software tools for EDA SP 1 OP 7 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3625223.3649280 DO https://dl.acm.org/doi/10.1145/3625223.3649280 SF ELIB - SuUB Bremen
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