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1 Ergebnisse
1
FPGA Implementation of Sequence Detector for High-Speed PAM..:
, In:
Proceedings of the Great Lakes Symposium on VLSI 2024
,
Xu, Chaolong
;
Lv, Fangxu
;
Pang, Zhengbin
.. - p. 13-18 , 2024
Link:
https://dl.acm.org/doi/10.1145/3649476.3658741
RT T1
Proceedings of the Great Lakes Symposium on VLSI 2024
: T1
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver
UL https://suche.suub.uni-bremen.de/peid=acm-3658741&Exemplar=1&LAN=DE A1 Xu, Chaolong A1 Lv, Fangxu A1 Pang, Zhengbin A1 Xiao, Liquan A1 Yang, Zhouhao PB ACM YR 2024 K1 FPGA K1 MLSD K1 PAM4 K1 Viterbi K1 Zero-forcing K1 set-partitioning K1 wireline transceiver K1 Hardware K1 Communication hardware, interfaces and storage K1 Signal processing systems K1 Digital signal processing SP 13 OP 18 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3649476.3658741 DO https://dl.acm.org/doi/10.1145/3649476.3658741 SF ELIB - SuUB Bremen
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