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Resource-Constraint Bayesian Optimization for Soft Processo..:

, In: Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,

Guo, Ce ; Wu, Haoran ; Luk, Wayne - p. 27-36 , 2024

Link: https://dl.acm.org/doi/10.1145/3665283.3665291

RT 
T1 <cTitle>Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</cTitle>: T1 <Title>Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-3665291&Exemplar=1&LAN=DE
				
A1 Guo, Ce
A1 Wu, Haoran
A1 Luk, Wayne
PB ACM
YR 2024
K1 Bayesian optimization
K1 FPGA
K1 parameter tuning
K1 parametric design
K1 resource constraint
K1 soft processor
K1 Hardware
K1 Integrated circuits
K1 Reconfigurable logic and FPGAs
K1 Evolvable hardware
K1 Electronic design automation
K1 Methodologies for EDA
K1 Software tools for EDA
K1 Computer systems organization
K1 Architectures
K1 Other architectures
K1 Reconfigurable computing
K1 High-level language architectures
K1 Serial architectures
K1 Reduced instruction set computing
K1 Self-organizing autonomic computing
K1 Embedded and cyber-physical systems
K1 Embedded systems
K1 Embedded hardware
SP 27
OP 36
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3665283.3665291
DO https://dl.acm.org/doi/10.1145/3665283.3665291
SF ELIB - SuUB Bremen

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