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1
Systolic Array-Based Many-Core Processor with Simultaneous ..:
, In:
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
,
Tan, Yuxi
;
Nishimura, Masaru
;
Abdelhamid, Riadh Ben
... - p. 119-125 , 2024
Link:
https://dl.acm.org/doi/10.1145/3665283.3665298
RT T1 <cTitle>Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</cTitle>: T1 <Title>Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3665298&Exemplar=1&LAN=DE A1 Tan, Yuxi A1 Nishimura, Masaru A1 Abdelhamid, Riadh Ben A1 Guo, Bingjie A1 Gao, Qixiang A1 Yamaguchi, Yoshiki PB ACM YR 2024 K1 MIMD K1 RISC-V K1 SIMD K1 Systolic arrays K1 manycore K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multiple instruction, multiple data K1 Multicore architectures K1 Systolic arrays K1 Single instruction, multiple data SP 119 OP 125 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3665283.3665298 DO https://dl.acm.org/doi/10.1145/3665283.3665298 SF ELIB - SuUB Bremen
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