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1 Ergebnisse
1
A Hardware Solver for Simultaneous Linear Equations with Mu..:
, In:
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
,
Tomii, Rikuya
;
Narumi, Tetsu
- p. 81-89 , 2024
Link:
https://dl.acm.org/doi/10.1145/3665283.3665299
RT T1 <cTitle>Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</cTitle>: T1 <Title>A Hardware Solver for Simultaneous Linear Equations with Multistage Interconnection Network</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3665299&Exemplar=1&LAN=DE A1 Tomii, Rikuya A1 Narumi, Tetsu PB ACM YR 2024 K1 FPGA K1 HPC K1 interconnection network K1 liner equations K1 Hardware K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Hardware accelerators K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multicore architectures SP 81 OP 89 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3665283.3665299 DO https://dl.acm.org/doi/10.1145/3665283.3665299 SF ELIB - SuUB Bremen
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