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VHDL modelling and analysis of fault secure systems:
, In:
Proceedings of the conference on Design, automation and test in Europe
,
Coppens, J.
;
Al-Khalili, D.
;
Rozon, C.
- p. 148-152 , 1998
Link:
https://dl.acm.org/doi/10.5555/368058.368124
RT T1 <cTitle>Proceedings of the conference on Design, automation and test in Europe</cTitle>: T1 <Title>VHDL modelling and analysis of fault secure systems</Title> UL https://suche.suub.uni-bremen.de/peid=acm-368124&Exemplar=1&LAN=DE A1 Coppens, J. A1 Al-Khalili, D. A1 Rozon, C. PB IEEE Computer Society YR 1998 K1 Defect Modelling K1 Fault Security K1 VHDL K1 Verification K1 Hardware K1 Electronic design automation K1 Hardware description languages and compilation K1 Networks K1 Network performance evaluation K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Computer systems organization K1 Dependable and fault-tolerant systems and networks K1 Robustness K1 Computing methodologies K1 Modeling and simulation K1 General and reference K1 Cross-computing tools and techniques K1 Performance SP 148 OP 152 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/368058.368124 DO https://dl.acm.org/doi/10.5555/368058.368124 SF ELIB - SuUB Bremen
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