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1 Ergebnisse
1
A new techology mapping for CPLD under the time constraint:
, In:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
,
Kim, Jae-Jin
;
Kim, Hi-Seok
;
Lin, Chi-Ho
- p. 235-238 , 2001
Link:
https://dl.acm.org/doi/10.1145/370155.370331
RT T1 <cTitle>Proceedings of the 2001 Asia and South Pacific Design Automation Conference</cTitle>: T1 <Title>A new techology mapping for CPLD under the time constraint</Title> UL https://suche.suub.uni-bremen.de/peid=acm-370331&Exemplar=1&LAN=DE A1 Kim, Jae-Jin A1 Kim, Hi-Seok A1 Lin, Chi-Ho PB ACM YR 2001 K1 feasible cluster K1 number of multi-level K1 technology mapping for CPLD K1 time constraint K1 Hardware K1 Integrated circuits K1 Mathematics of computing K1 Discrete mathematics K1 Robustness K1 General and reference K1 Cross-computing tools and techniques K1 Performance K1 Computer systems organization K1 Dependable and fault-tolerant systems and networks K1 Applied computing K1 Physical sciences and engineering K1 Electronics K1 Networks K1 Network performance evaluation SP 235 OP 238 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/370155.370331 DO https://dl.acm.org/doi/10.1145/370155.370331 SF ELIB - SuUB Bremen
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