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1 Ergebnisse
1
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 c..:
, In:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
,
Grodstein, Joel
;
Rayess, Rachid
;
Truex, Tad
... - p. 1-6 , 2002
Link:
https://dl.acm.org/doi/10.1145/505306.505308
RT T1 <cTitle>Proceedings of the 12th ACM Great Lakes symposium on VLSI</cTitle>: T1 <Title>Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU</Title> UL https://suche.suub.uni-bremen.de/peid=acm-505308&Exemplar=1&LAN=DE A1 Grodstein, Joel A1 Rayess, Rachid A1 Truex, Tad A1 Shattuck, Linda A1 Lowell, Sue A1 Bailey, Dan A1 Bertucci, David A1 Bischoff, Gabriel A1 Dever, Daniel A1 Gowan, Mike A1 Lane, Roy A1 Lilly, Brian A1 Nagalla, Krishna A1 Shah, Rahul A1 Shriver, Emily A1 Yin, Shi-Huang A1 Morton, Shannon PB ACM YR 2002 K1 CPU K1 cache memory K1 logic verification K1 low-power K1 timing verification K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Static memory K1 Dynamic memory SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/505306.505308 DO https://dl.acm.org/doi/10.1145/505306.505308 SF ELIB - SuUB Bremen
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