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1 Ergebnisse
1
Petri net modeling of gate and interconnect delays for powe..:
, In:
Proceedings of the 39th annual Design Automation Conference
,
Murugavel, Ashok K.
;
Ranganathan, N.
- p. 455-460 , 2002
Link:
https://dl.acm.org/doi/10.1145/513918.514034
RT T1 <cTitle>Proceedings of the 39th annual Design Automation Conference</cTitle>: T1 <Title>Petri net modeling of gate and interconnect delays for power estimation</Title> UL https://suche.suub.uni-bremen.de/peid=acm-514034&Exemplar=1&LAN=DE A1 Murugavel, Ashok K. A1 Ranganathan, N. PB ACM YR 2002 K1 Hardware K1 Integrated circuits K1 Hardware validation K1 Functional verification K1 Simulation and emulation SP 455 OP 460 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/513918.514034 DO https://dl.acm.org/doi/10.1145/513918.514034 SF ELIB - SuUB Bremen
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