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1
On the inclusion properties for multi-level cache hierarchi..:
, In:
Proceedings of the 15th Annual International Symposium on Computer architecture
,
Baer, J.-L.
;
Wang, W.-H.
- p. 73-80 , 1988
Link:
https://dl.acm.org/doi/10.5555/52400.52409
RT T1
Proceedings of the 15th Annual International Symposium on Computer architecture
: T1
On the inclusion properties for multi-level cache hierarchies
UL https://suche.suub.uni-bremen.de/peid=acm-52409&Exemplar=1&LAN=DE A1 Baer, J.-L. A1 Wang, W.-H. PB IEEE Computer Society Press YR 1988 K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multiple instruction, multiple data SP 73 OP 80 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/52400.52409 DO https://dl.acm.org/doi/10.5555/52400.52409 SF ELIB - SuUB Bremen
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