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The optimal logic depth per pipeline stage is 6 to 8 FO4 in..:

, In: Proceedings of the 29th annual international symposium on Computer architecture,
Hrishikesh, M. S. ; Burger, Doug ; Jouppi, Norman P.... - p. 14-24 , 2002
Link: https://dl.acm.org/doi/10.5555/545215.545218