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A two-tier memory architecture for high-performance multipr..:

, In: Proceedings of the 2nd international conference on Supercomputing,

Nguyen, T. M. ; Srini, V. P. ; Despain, A. M. - p. 326-336 , 1988

Link: https://dl.acm.org/doi/10.1145/55364.55396

RT 
T1 <cTitle>Proceedings of the 2nd international conference on Supercomputing</cTitle>: T1 <Title>A two-tier memory architecture for high-performance multiprocessor systems</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-55396&Exemplar=1&LAN=DE
				
A1 Nguyen, T. M.
A1 Srini, V. P.
A1 Despain, A. M.
PB ACM
YR 1988
K1 Computer systems organization
K1 Architectures
K1 Computing methodologies
K1 Artificial intelligence
K1 Knowledge representation and reasoning
K1 Software and its engineering
K1 Software notations and tools
K1 General programming languages
K1 Language types
K1 Software organization and properties
K1 Software system structures
K1 Distributed systems organizing principles
K1 Grid computing
K1 Parallel architectures
K1 Systolic arrays
K1 Serial architectures
K1 Superscalar architectures
K1 Distributed architectures
K1 Multicore architectures
K1 Interconnection architectures
K1 Symbolic and algebraic manipulation
K1 Symbolic and algebraic algorithms
K1 Theorem proving algorithms
K1 Modeling and simulation
K1 Simulation types and techniques
K1 Massively parallel and high-performance simulations
SP 326
OP 336
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/55364.55396
DO https://dl.acm.org/doi/10.1145/55364.55396
SF ELIB - SuUB Bremen

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