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1 Ergebnisse
1
HA2TSD : hierarchical time slack distribution for ultra-..:
, In:
Proceedings of the 2002 international symposium on Low power electronics and design
,
Choi, Kyu-won
;
Chatterjee, Abhijit
- p. 207-212 , 2002
Link:
https://dl.acm.org/doi/10.1145/566408.566459
RT T1 <cTitle>Proceedings of the 2002 international symposium on Low power electronics and design</cTitle>: T1 <Title>HA2TSD : hierarchical time slack distribution for ultra-low power CMOS VLSI</Title> UL https://suche.suub.uni-bremen.de/peid=acm-566459&Exemplar=1&LAN=DE A1 Choi, Kyu-won A1 Chatterjee, Abhijit PB ACM YR 2002 K1 gate-level power optimization K1 low-power design K1 time slack distribution K1 Hardware K1 Hardware validation K1 Functional verification K1 Simulation and emulation SP 207 OP 212 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/566408.566459 DO https://dl.acm.org/doi/10.1145/566408.566459 SF ELIB - SuUB Bremen
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