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1
Delay models for the sea-of-wires array synthesis system:
, In:
Proceedings of the 1995 European conference on Design and Test
,
Chen, Ing-Yi
;
Chen, Geng-Lin
;
Kuo, Sy-Yen
- p. 228 ff. , 1995
Link:
https://dl.acm.org/doi/10.5555/787258.787441
RT T1 <cTitle>Proceedings of the 1995 European conference on Design and Test</cTitle>: T1 <Title>Delay models for the sea-of-wires array synthesis system</Title> UL https://suche.suub.uni-bremen.de/peid=acm-787441&Exemplar=1&LAN=DE A1 Chen, Ing-Yi A1 Chen, Geng-Lin A1 Kuo, Sy-Yen PB IEEE Computer Society YR 1995 K1 VLSI K1 attribute-based primitive gate K1 circuit optimisation K1 circuit path K1 connection wires K1 delays K1 differential equations K1 distributed gate K1 dynamic delay model K1 error margin K1 logic CAD K1 logic arrays K1 multi-dimensional table lookup K1 performance optimization K1 propagation delay K1 sea-of-wires array synthesis K1 static delay model K1 table lookup K1 timing K1 timing analysis algorithm K1 Hardware K1 Very large scale integration design K1 Hardware validation SP 228 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/787258.787441 DO https://dl.acm.org/doi/10.5555/787258.787441 SF ELIB - SuUB Bremen
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