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Automatic fault extraction and simulation of layout realist..:

, In: Proceedings of the 1995 European conference on Design and Test,

Sebeke, C. ; Teixeira, J. P. ; Ohletz, M. J. - p. 464 ff. , 1995

Link: https://dl.acm.org/doi/10.5555/787258.787477

RT 
T1 <cTitle>Proceedings of the 1995 European conference on Design and Test</cTitle>: T1 <Title>Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-787477&Exemplar=1&LAN=DE
				
A1 Sebeke, C.
A1 Teixeira, J. P.
A1 Ohletz, M. J.
PB IEEE Computer Society
YR 1995
K1 AnaFAUL
K1 LIFT
K1 VCO
K1 analogue integrated circuits
K1 automatic analogue fault simulation program
K1 catastrophic faults
K1 circuit analysis computing
K1 circuit layout
K1 fault diagnosis
K1 integrated analogue circuits
K1 integrated circuit layout
K1 integrated circuit testing
K1 mixed analogue-digital integrated circuits
K1 mixed-signal circuit
K1 parametric faults
K1 realistic fault characterisation program
K1 simulation
K1 test preparation
K1 voltage-controlled oscillators
K1 Hardware
K1 Very large scale integration design
K1 Hardware validation
K1 Hardware test
K1 Robustness
K1 Emerging technologies
SP 464 ff.
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/787258.787477
DO https://dl.acm.org/doi/10.5555/787258.787477
SF ELIB - SuUB Bremen

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