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A built-in quiescent current monitor for CMOS VLSI circuits:

, In: Proceedings of the 1995 European conference on Design and Test,

Rubio, A. ; Janssens, E. ; Casier, H.... - p. 581 ff. , 1995

Link: https://dl.acm.org/doi/10.5555/787258.787497

RT 
T1 <cTitle>Proceedings of the 1995 European conference on Design and Test</cTitle>: T1 <Title>A built-in quiescent current monitor for CMOS VLSI circuits</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-787497&Exemplar=1&LAN=DE
				
A1 Rubio, A.
A1 Janssens, E.
A1 Casier, H.
A1 Figueras, J.
A1 Mateo, D.
A1 De Pauw, P.
A1 Segura, J.
PB IEEE Computer Society
YR 1995
K1 ASIC
K1 BIC monitor
K1 CMOS VLSI circuits
K1 CMOS digital integrated circuits
K1 I/sub DDQ/ current level
K1 VLSI
K1 application specific integrated circuits
K1 automatic recovery mechanism
K1 built-in quiescent current monitor
K1 built-in self test
K1 digital IC tester
K1 electric current measurement
K1 integrated circuit testing
K1 power supply voltage perturbation
K1 Hardware
K1 Very large scale integration design
K1 Hardware validation
K1 Hardware test
K1 Robustness
K1 Emerging technologies
SP 581 ff.
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/787258.787497
DO https://dl.acm.org/doi/10.5555/787258.787497
SF ELIB - SuUB Bremen

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