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Multi-layer chip-level global routing using an efficient gr..:

, In: Proceedings of the 1997 European conference on Design and Test,

Liu, Le-Chin Eugene ; Sechen, C. - p. 311 ff. , 1997

Link: https://dl.acm.org/doi/10.5555/787260.787682

RT 
T1 <cTitle>Proceedings of the 1997 European conference on Design and Test</cTitle>: T1 <Title>Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-787682&Exemplar=1&LAN=DE
				
A1 Liu, Le-Chin Eugene
A1 Sechen, C.
PB IEEE Computer Society
YR 1997
K1 3D mixed directed/undirected routing graph
K1 NP-hard problem
K1 Steiner minimum trees
K1 Steiner tree heuristic algorithm
K1 chip-level global routing
K1 global routing model
K1 graph-based Steiner tree heuristic
K1 large routing graphs
K1 multilayer macro-cell technology
K1 multilayer routing problem
K1 network routing
K1 routing resource congestion problems
K1 space complexity
K1 time complexity
K1 vias minimisation
K1 wire length minimisation
K1 Mathematics of computing
K1 Discrete mathematics
K1 Graph theory
K1 Graph algorithms
K1 Theory of computation
K1 Design and analysis of algorithms
K1 Approximation algorithms analysis
K1 Routing and network design problems
SP 311 ff.
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/787260.787682
DO https://dl.acm.org/doi/10.5555/787260.787682
SF ELIB - SuUB Bremen

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