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1
Maximizing the weighted switching activity in combinational..:
, In:
Proceedings of the 1997 European conference on Design and Test
,
Manich, S.
;
Figueras, J.
- p. 597 ff. , 1997
Link:
https://dl.acm.org/doi/10.5555/787260.787726
RT T1 <cTitle>Proceedings of the 1997 European conference on Design and Test</cTitle>: T1 <Title>Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model</Title> UL https://suche.suub.uni-bremen.de/peid=acm-787726&Exemplar=1&LAN=DE A1 Manich, S. A1 Figueras, J. PB IEEE Computer Society YR 1997 K1 CMOS logic circuits K1 ISCAS-85 benchmark circuits K1 combinational CMOS circuits K1 fault testing problem K1 maximization problem K1 maximum weighted switching activity K1 pseudo-random sample simulation K1 simulation time K1 test vectors K1 variable delay model K1 weighted switching activity K1 Hardware K1 Very large scale integration design K1 Hardware validation K1 Hardware test K1 Robustness SP 597 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/787260.787726 DO https://dl.acm.org/doi/10.5555/787260.787726 SF ELIB - SuUB Bremen
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