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1 Ergebnisse
1
Hierarchical design verification for large digital systems:
, In:
Proceedings of the 18th Design Automation Conference
,
Sasaki, Tohru
;
Yamada, Akihiko
;
Aoyama, Toshinori
... - p. 105-112 , 1981
Link:
https://dl.acm.org/doi/10.5555/800073.802287
RT T1 <cTitle>Proceedings of the 18th Design Automation Conference</cTitle>: T1 <Title>Hierarchical design verification for large digital systems</Title> UL https://suche.suub.uni-bremen.de/peid=acm-802287&Exemplar=1&LAN=DE A1 Sasaki, Tohru A1 Yamada, Akihiko A1 Aoyama, Toshinori A1 Hasegawa, Katsutoshi A1 Kato, Shunichi A1 Sato, Shinichi PB IEEE Press YR 1981 K1 Software and its engineering K1 Software creation and management K1 Designing software K1 Software organization and properties K1 Contextual software domains K1 Operating systems K1 Hardware K1 Hardware validation K1 Functional verification K1 Mathematics of computing K1 Mathematical analysis K1 Integral equations SP 105 OP 112 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/800073.802287 DO https://dl.acm.org/doi/10.5555/800073.802287 SF ELIB - SuUB Bremen
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