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Verification and optimization for LSI & PCB layout:
, In:
Proceedings of the 18th Design Automation Conference
,
Brady, H. Nelson
;
Smith II, Robert J.
- p. 365-371 , 1981
Link:
https://dl.acm.org/doi/10.5555/800073.802331
RT T1 <cTitle>Proceedings of the 18th Design Automation Conference</cTitle>: T1 <Title>Verification and optimization for LSI & PCB layout</Title> UL https://suche.suub.uni-bremen.de/peid=acm-802331&Exemplar=1&LAN=DE A1 Brady, H. Nelson A1 Smith II, Robert J. PB IEEE Press YR 1981 K1 Hardware K1 Hardware validation K1 Functional verification K1 Electronic design automation K1 Logic synthesis K1 Circuit optimization K1 Very large scale integration design K1 Application-specific VLSI designs K1 Theory of computation K1 Design and analysis of algorithms K1 Approximation algorithms analysis K1 Routing and network design problems K1 Physical design (EDA) K1 Partitioning and floorplanning SP 365 OP 371 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/800073.802331 DO https://dl.acm.org/doi/10.5555/800073.802331 SF ELIB - SuUB Bremen
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