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LOTOS Code Generation for Model Checking of STBus Based SoC..:

, In: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design,

Wodey, Pierre ; Camarroque, Geoffrey ; Hersemeule, Richard. - p. 204 ff. , 2003

Link: https://dl.acm.org/doi/10.5555/823453.823850

RT 
T1 <cTitle>Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design</cTitle>: T1 <Title>LOTOS Code Generation for Model Checking of STBus Based SoC				: the STBus interconnect</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-823850&Exemplar=1&LAN=DE
				
A1 Wodey, Pierre
A1 Camarroque, Geoffrey
A1 Hersemeule, Richard
A1 Cousin, Jean-Philippe
PB IEEE Computer Society
YR 2003
K1 Hardware
K1 Very large scale integration design
K1 Application-specific VLSI designs
K1 Application specific processors
K1 Software and its engineering
K1 Software creation and management
K1 Software verification and validation
K1 Communication hardware, interfaces and storage
K1 Buses and high-speed links
K1 Process validation
K1 Computer systems organization
K1 Architectures
K1 Parallel architectures
K1 Interconnection architectures
K1 Empirical software validation
K1 General and reference
K1 Cross-computing tools and techniques
K1 Validation
SP 204 ff.
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/823453.823850
DO https://dl.acm.org/doi/10.5555/823453.823850
SF ELIB - SuUB Bremen

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