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Modeling of Short Circuit Power Consumption Using Timing-On..:

, In: Proceedings of the 13th symposium on Integrated circuits and systems design,

da Costa, E. A. C. ; Cortes, F. P. ; Cardoso, R... - p. 222 ff. , 2000

Link: https://dl.acm.org/doi/10.5555/827245.827320

RT 
T1 <cTitle>Proceedings of the 13th symposium on Integrated circuits and systems design</cTitle>: T1 <Title>Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-827320&Exemplar=1&LAN=DE
				
A1 da Costa, E. A. C.
A1 Cortes, F. P.
A1 Cardoso, R.
A1 Carro, L.
A1 Bampi, S.
PB IEEE Computer Society
YR 2000
K1 CMOS gates
K1 CMOS logic circuits
K1 adders
K1 analytical modeling
K1 buffers
K1 cell-oriented logic synthesis
K1 delay estimation
K1 delays
K1 dynamic power estimation
K1 input transition times
K1 integrated circuit modelling
K1 logic design
K1 logic gates
K1 output loading factor
K1 power components
K1 power supply voltage
K1 short circuit power consumption
K1 short circuit power dissipation
K1 signal slopes
K1 timing
K1 timing analysis
K1 timing parameters
K1 timing-only logic cell macromodels
K1 Hardware
K1 Very large scale integration design
K1 Hardware validation
SP 222 ff.
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/827245.827320
DO https://dl.acm.org/doi/10.5555/827245.827320
SF ELIB - SuUB Bremen

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