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1 Ergebnisse
1
Task-level timing models for guaranteed performance in mult..:
, In:
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
,
Poplavko, P.
;
Basten, T.
;
Bekooij, M.
.. - p. 63-72 , 2003
Link:
https://dl.acm.org/doi/10.1145/951710.951721
RT T1
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
: T1
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
UL https://suche.suub.uni-bremen.de/peid=acm-951721&Exemplar=1&LAN=DE A1 Poplavko, P. A1 Basten, T. A1 Bekooij, M. A1 van Meerbergen, J. A1 Mesman, B. PB ACM YR 2003 K1 buffer minimization K1 data flow graph K1 network-on-chip K1 performance evaluation K1 real-time K1 system-on-chip K1 Hardware K1 Hardware validation SP 63 OP 72 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/951710.951721 DO https://dl.acm.org/doi/10.1145/951710.951721 SF ELIB - SuUB Bremen
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