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Modeling and Simulating Memory Hierarchies in a Platform-Ba..:
, In:
Proceedings of the conference on Design, automation and test in Europe - Volume 1
,
Viana, Pablo
;
Barros, Edna
;
Rigo, Sandro
.. - p. 10734 ff. , 2004
Link:
https://dl.acm.org/doi/10.5555/968878.969012
RT T1 <cTitle>Proceedings of the conference on Design, automation and test in Europe - Volume 1</cTitle>: T1 <Title>Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology</Title> UL https://suche.suub.uni-bremen.de/peid=acm-969012&Exemplar=1&LAN=DE A1 Viana, Pablo A1 Barros, Edna A1 Rigo, Sandro A1 Azevedo, Rodolfo A1 Araújo, Guido PB IEEE Computer Society YR 2004 K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Integrated circuits K1 Semiconductor memory K1 Hardware description languages and compilation K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Computing methodologies K1 Modeling and simulation K1 Model development and analysis K1 Modeling methodologies SP 10734 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/968878.969012 DO https://dl.acm.org/doi/10.5555/968878.969012 SF ELIB - SuUB Bremen
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