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Design methodology for semi custom processor cores:
, In:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
,
Zyuban, Victor
;
Asaad, Sameh W.
;
Fox, Thomas W.
... - p. 448-452 , 2004
Link:
https://dl.acm.org/doi/10.1145/988952.989060
RT T1 <cTitle>Proceedings of the 14th ACM Great Lakes symposium on VLSI</cTitle>: T1 <Title>Design methodology for semi custom processor cores</Title> UL https://suche.suub.uni-bremen.de/peid=acm-989060&Exemplar=1&LAN=DE A1 Zyuban, Victor A1 Asaad, Sameh W. A1 Fox, Thomas W. A1 Haen, Anne-Marie A1 Littrell, Daniel A1 Moreno, Jaime H. PB ACM YR 2004 K1 ASIC K1 core K1 design K1 methodology K1 microprocessor K1 synthesis K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Datapath optimization K1 Physical design (EDA) K1 Partitioning and floorplanning K1 Wire routing K1 Hardware validation K1 Placement SP 448 OP 452 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/988952.989060 DO https://dl.acm.org/doi/10.1145/988952.989060 SF ELIB - SuUB Bremen
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