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1 Ergebnisse
1
Low Power Digital Clock Design Using LVCMOS Input/Output St..:
Pandey, Sujeet
;
Mehta, Rishabh
;
Kalia, Kartik
...
https://vbn.aau.dk/da/publications/f44c2a17-1245-4d4d-aee6-7d5017c0417e. , 2016
Link:
https://vbn.aau.dk/da/publications/f44c2a17-1245-4d4d-..
RT Journal T1
Low Power Digital Clock Design Using LVCMOS Input/Output Standards on 45nm FPGA
UL https://suche.suub.uni-bremen.de/peid=base-ftalborgunivpubl:oai:pure.atira.dk:publications_f44c2a17-1245-4d4d-aee6-7d5017c0417e&Exemplar=1&LAN=DE A1 Pandey, Sujeet A1 Mehta, Rishabh A1 Kalia, Kartik A1 Khanna, Anirudh A1 Hussain, Dil muhammed Akbar A1 Verma, Gaurav YR 2016 K1 Power K1 Efficient K1 LVCMOS K1 Digital Clock K1 FPGA JF https://vbn.aau.dk/da/publications/f44c2a17-1245-4d4d-aee6-7d5017c0417e LK http://dx.doi.org/https://vbn.aau.dk/da/publications/f44c2a17-1245-4d4d-aee6-7d5017c0417e DO https://vbn.aau.dk/da/publications/f44c2a17-1245-4d4d-aee6-7d5017c0417e SF ELIB - SuUB Bremen
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