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1 Ergebnisse
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A Template-Based Design Methodology for Graph-Parallel Hard..:
Ayupov, A
;
Yesil, S
;
Ozdal, M. M
...
info:eu-repo/grantAgreement/EC/H2020/704476/. , 2017
Link:
http://hdl.handle.net/11693/46922
RT Journal T1 <Title>A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators</Title> UL https://suche.suub.uni-bremen.de/peid=base-ftbilkentuniv:oai:repository.bilkent.edu.tr:11693_46922&Exemplar=1&LAN=DE A1 Ayupov, A A1 Yesil, S A1 Ozdal, M. M A1 Kim, T A1 Burns, S A1 Ozturk, O PB Institute of Electrical and Electronics Engineers Inc. YR 2017 K1 Acceleration K1 Big data K1 Hardware K1 High level synthesis K1 Program processors JF info:eu-repo/grantAgreement/EC/H2020/704476/ LK http://hdl.handle.net/11693/46922 DO http://hdl.handle.net/11693/46922 SF ELIB - SuUB Bremen
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