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1 Ergebnisse
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Accelerator-Driven Data Arrangement to Minimize Transformer..:
Amirshahi, Alireza
;
Ansaloni, Giovanni
;
Atienza, David
Is Part Of OASIcs, Volume 116, 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024). , 2024
Link:
https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.2
RT Journal T1 <Title>Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures</Title> UL https://suche.suub.uni-bremen.de/peid=base-ftdagstuhl:oai:drops-oai.dagstuhl.de:19696&Exemplar=1&LAN=DE A1 Amirshahi, Alireza A1 Ansaloni, Giovanni A1 Atienza, David PB Schloss Dagstuhl – Leibniz-Zentrum für Informatik YR 2024 K1 Memory arrangement K1 Data layout K1 Hardware accelerators K1 Transformer models K1 Multi-core K1 System simulation JF Is Part Of OASIcs, Volume 116, 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024) LK http://dx.doi.org/https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.2 DO https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.2 SF ELIB - SuUB Bremen
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