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1 Ergebnisse
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A dynamic reconfigurable architecture for hybrid spiking an..:
Irmak, Hasan
;
Corradi, Federico
;
Detterer, Paul
..
Journal of Low Power Electronics and Applications -- 2079-9268 -- http://uri.gbv.de/document/gvk:ppn:718295641 -- 2662567-2 -- http://www.mdpi.com/journal/jlpea -- http://www.bibliothek.uni-regensburg.de/ezeit/?2662567. , 2021
Link:
https://doi.org/10.3390/jlpea11030032
RT Journal T1 <Title>A dynamic reconfigurable architecture for hybrid spiking and convolutional FPGA-based neural network designs</Title> UL https://suche.suub.uni-bremen.de/peid=base-ftdbthueringen:oai:www.db-thueringen.de:dbt_mods_00051958&Exemplar=1&LAN=DE A1 Irmak, Hasan A1 Corradi, Federico A1 Detterer, Paul A1 Alachiotis, Nikolaos A1 Ziener, Daniel YR 2021 K1 article K1 ScholarlyArticle K1 ddc:530 K1 FPGA -- NN -- CNN -- SNN -- partial reconfiguration JF Journal of Low Power Electronics and Applications -- 2079-9268 -- http://uri.gbv.de/document/gvk:ppn:718295641 -- 2662567-2 -- http://www.mdpi.com/journal/jlpea -- http://www.bibliothek.uni-regensburg.de/ezeit/?2662567 LK http://dx.doi.org/https://doi.org/10.3390/jlpea11030032 DO https://doi.org/10.3390/jlpea11030032 SF ELIB - SuUB Bremen
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