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1 Ergebnisse
1
Analysis of Logic Gates for Generation of Switching Sequenc..:
Kanike Vinod Kumar
;
R. Saravana Kumar
https://ieeexplore.ieee.org/document/8766796/. , 2019
Link:
https://doi.org/10.1109/ACCESS.2019.2929836
RT Journal T1
Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter
UL https://suche.suub.uni-bremen.de/peid=base-ftdoajarticles:oai:doaj.org_article:29eb35cf49284798b2ce8ae39bcd68a4&Exemplar=1&LAN=DE A1 Kanike Vinod Kumar A1 R. Saravana Kumar PB IEEE YR 2019 K1 5 switch module K1 8 switch module K1 logic gates K1 multilevel inverter K1 pulse pattern K1 multi carrier sinusoidal pulse width modulation K1 Electrical engineering. Electronics. Nuclear engineering K1 TK1-9971 JF https://ieeexplore.ieee.org/document/8766796/ LK http://dx.doi.org/https://doi.org/10.1109/ACCESS.2019.2929836 DO https://doi.org/10.1109/ACCESS.2019.2929836 SF ELIB - SuUB Bremen
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