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1 Ergebnisse
1
Test Scheduling and Test Time Minimization of System-on-Chi..:
Gokul Chandrasekaran
;
Neelam Sanjeev Kumar
;
P. R. Karthikeyan
...
https://ieeexplore.ieee.org/document/9964215/. , 2022
Link:
https://doi.org/10.1109/ACCESS.2022.3224924
RT Journal T1
Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm
UL https://suche.suub.uni-bremen.de/peid=base-ftdoajarticles:oai:doaj.org_article:73ca7673ca364541893bfc5572bf78f0&Exemplar=1&LAN=DE A1 Gokul Chandrasekaran A1 Neelam Sanjeev Kumar A1 P. R. Karthikeyan A1 K. Vanchinathan A1 Neeraj Priyadarshi A1 Bhekisipho Twala PB IEEE YR 2022 K1 Test time K1 system-on-chip K1 modified BAT algorithm K1 BAT algorithm K1 test scheduling K1 Electrical engineering. Electronics. Nuclear engineering K1 TK1-9971 JF https://ieeexplore.ieee.org/document/9964215/ LK http://dx.doi.org/https://doi.org/10.1109/ACCESS.2022.3224924 DO https://doi.org/10.1109/ACCESS.2022.3224924 SF ELIB - SuUB Bremen
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