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Design of a Low - power CMOS Level Shifter for Low - delay ..:
Mohammad Torikul Islam Badal
;
Mamun Bin Ibne Reaz
;
Araf Farayez
..
http://www.jestr.org/downloads/Volume10Issue4/fulltext21042017.pdf. , 2017
Link:
https://doi.org/10.25103/jestr.104.02
RT Journal T1
Design of a Low - power CMOS Level Shifter for Low - delay SoCs in Silterra 0.13 μm CMOS Process
UL https://suche.suub.uni-bremen.de/peid=base-ftdoajarticles:oai:doaj.org_article:8261452ad0d643cd9d8bd1cf373e3eba&Exemplar=1&LAN=DE A1 Mohammad Torikul Islam Badal A1 Mamun Bin Ibne Reaz A1 Araf Farayez A1 Siti A. B. Ramli A1 Noorfazila Kamal PB Eastern Macedonia and Thrace Institute of Technology YR 2017 K1 Engineering (General). Civil engineering (General) K1 TA1-2040 K1 Technology (General) K1 T1-995 JF http://www.jestr.org/downloads/Volume10Issue4/fulltext21042017.pdf LK http://dx.doi.org/https://doi.org/10.25103/jestr.104.02 DO https://doi.org/10.25103/jestr.104.02 SF ELIB - SuUB Bremen
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