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1 Ergebnisse
1
A power-efficient pipeline based clock gating FIFO for a du..:
S. Dhanasekar
;
V. Govindaraj
;
P. Malin Bruntha
.
https://sjst.psu.ac.th/journal/45-2/3.pdf. , 2023
Link:
https://doaj.org/article/8975e353f17e4638a1e3939c0d524..
RT Journal T1
A power-efficient pipeline based clock gating FIFO for a dual ported memory array
UL https://suche.suub.uni-bremen.de/peid=base-ftdoajarticles:oai:doaj.org_article:8975e353f17e4638a1e3939c0d524324&Exemplar=1&LAN=DE A1 S. Dhanasekar A1 V. Govindaraj A1 P. Malin Bruntha A1 L. Jubair Ahmed PB Prince of Songkla University YR 2023 K1 synchronous fifo K1 pipeline K1 clock gating K1 read K1 write K1 Technology K1 T K1 Technology (General) K1 T1-995 K1 Science K1 Q K1 Science (General) K1 Q1-390 JF https://sjst.psu.ac.th/journal/45-2/3.pdf LK http://dx.doi.org/https://doaj.org/article/8975e353f17e4638a1e3939c0d524324 DO https://doaj.org/article/8975e353f17e4638a1e3939c0d524324 SF ELIB - SuUB Bremen
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