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1 Ergebnisse
1
Low-Power High-Speed Double Gate 1-bit Full Adder Cell:
Kumar, Raushan
;
Roy, Sahadev
;
Bhunia, Chandan Tilak
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0045/324. , 2016
Link:
http://ijet.pl/index.php/ijet/article/view/10.1515-ele..
RT Journal T1
Low-Power High-Speed Double Gate 1-bit Full Adder Cell
UL https://suche.suub.uni-bremen.de/peid=base-ftjijet:oai:ojs.ijet.ise.pw.edu.pl:article_516&Exemplar=1&LAN=DE A1 Kumar, Raushan A1 Roy, Sahadev A1 Bhunia, Chandan Tilak PB Electronics and Telecommunications Committee YR 2016 K1 Low-power full-adder K1 Low-power CMOS design K1 multiplexer based full-adder design K1 multi-threshold voltage based Full-adder design K1 pass transmission logic JF http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0045/324 LK http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0045 DO http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0045 SF ELIB - SuUB Bremen
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