Fan, Qingjun
Portions of this document appear in: Fan, Qingjun, and Jinghong Chen. "A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology." IEEE Solid-State Circuits Letters 2, no. 9 (2019): 99-102. And in: Fan, Qingjun, Runxi Zhang, Phaneendra Bikkina, Esko Mikkola, and Jinghong Chen. "A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator." In ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp. 193-196. IEEE, 2019. And in: Fan, Qingjun, and Jinghong Chen. "A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration." In ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp. 301-304. IEEE, 2019. And in: Fan, Qingjun, Yi Hong, and Jinghong Chen. "A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration." IEEE Journal of Solid-State Circuits (2020)..  , 2020