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Inertial and Degradation Delay Model for CMOS Logic Gates:

Juan Chico, Jorge ; Ruiz de Clavijo Vázquez, Paulino ; Bellido Díaz, Manuel Jesús..
ISCAS 2000: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (2000), p I-459-I-462.  , 2018
Link: https://idus.us.es/handle//11441/77511