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1 Ergebnisse
1
Generación automática de verificación en System Verilog de ..:
López Azcona, Lucas
;
Navarro Tabernero, Denis
;
Resano Ezcaray, Jesús Javier
http://zaguan.unizar.es/record/61115. , 2016
Link:
http://zaguan.unizar.es/record/61115
RT Journal T1
Generación automática de verificación en System Verilog de un banco de registros VHDL
UL https://suche.suub.uni-bremen.de/peid=base-ftunivzaraaneto:oai:zaguan.unizar.es:61115&Exemplar=1&LAN=DE A1 López Azcona, Lucas A1 Navarro Tabernero, Denis A1 Resano Ezcaray, Jesús Javier PB Universidad de Zaragoza YR 2016 JF http://zaguan.unizar.es/record/61115 LK http://zaguan.unizar.es/record/61115 DO http://zaguan.unizar.es/record/61115 SF ELIB - SuUB Bremen
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