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1 Ergebnisse
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Circuit design of a novel adaptable and reliable L1 data ca..:
Seyedi, Azam
;
Yalcin, Gulay
;
Unsal, Osman Sabri
.
info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC. , 2013
Link:
http://hdl.handle.net/2117/23133
RT Journal T1
Circuit design of a novel adaptable and reliable L1 data cache
UL https://suche.suub.uni-bremen.de/peid=base-ftupcatalunyair:oai:upcommons.upc.edu:2117_23133&Exemplar=1&LAN=DE A1 Seyedi, Azam A1 Yalcin, Gulay A1 Unsal, Osman Sabri A1 Cristal Kestelman, Adrián YR 2013 K1 Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació K1 Cache memory K1 CMOS integrated circuits K1 Design K1 Electric power supplies to apparatus K1 Fault tolerance K1 Fault tolerant computer systems K1 Separation K1 Memòria cau JF info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC LK http://hdl.handle.net/2117/23133 DO http://hdl.handle.net/2117/23133 SF ELIB - SuUB Bremen
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