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SafeSU: an extended statistics unit for multicore timing in..:
Cabo Pitarch, Guillem
;
Bas Jalón, Francisco
;
Lorenzo Ortega, Rubén
...
https://ieeexplore.ieee.org/document/9465444. , 2021
Link:
http://hdl.handle.net/2117/352123
RT Journal T1
SafeSU: an extended statistics unit for multicore timing interference
UL https://suche.suub.uni-bremen.de/peid=base-ftupcatalunyair:oai:upcommons.upc.edu:2117_352123&Exemplar=1&LAN=DE A1 Cabo Pitarch, Guillem A1 Bas Jalón, Francisco A1 Lorenzo Ortega, Rubén A1 Trilla Rodríguez, David A1 Alcaide Portet, Sergi A1 Moreto Planas, Miquel A1 Hernández Luz, Carles A1 Abella Ferrer, Jaume PB Institute of Electrical and Electronics Engineers (IEEE) YR 2021 K1 Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors K1 Multiprocessors K1 Real-time data processing K1 Safety K1 Observability K1 Controllability K1 MPSoC K1 Multiprocessadors K1 Temps real (Informàtica) JF https://ieeexplore.ieee.org/document/9465444 LK http://hdl.handle.net/2117/352123 DO http://hdl.handle.net/2117/352123 SF ELIB - SuUB Bremen
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