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1 Ergebnisse
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DVINO: A RISC-V vector processor implemented in 65nm techno..:
Cabo Pitarch, Guillem
;
Candon, Gerard
;
Carril, Xavier
...
https://ieeexplore.ieee.org/document/9970128. , 2022
Link:
http://hdl.handle.net/2117/382730
RT Journal T1
DVINO: A RISC-V vector processor implemented in 65nm technology
UL https://suche.suub.uni-bremen.de/peid=base-ftupcatalunyair:oai:upcommons.upc.edu:2117_382730&Exemplar=1&LAN=DE A1 Cabo Pitarch, Guillem A1 Candon, Gerard A1 Carril, Xavier A1 Doblas Font, Max A1 Dominguez de la Rocha, Marc A1 González Trejo, Alberto A1 Hernández Calderón, César Alejandro A1 Jiménez Arador, Víctor A1 Kostalampros, Ioannis-Vatistas A1 Langarita Benítez, Rubén A1 Leyva Santes, Neiel Israel A1 López Paradís, Guillem A1 Mendoza Escobar, Jonnatan A1 Minervini Minervini, Francesco A1 Pavón Rivera, Julián A1 Ramírez Lazo, Cristóbal A1 Rodas, Narcis A1 Reggiani, Enrico A1 Rodriguez, Mario A1 Rojas Morales, Carlos A1 Ruíz Ramírez, Abraham Josafat A1 Soria Pardos, Víctor A1 Vargas Valdivieso, Iván A1 Figueras Bagué, Roger A1 Fontova, Pau A1 Marimon Illana, Joan A1 Montabes, Víctor A1 Cristal Kestelman, Adrián A1 Hernández Luz, Carles A1 Moreto Planas, Miquel A1 Moll Echeto, Francisco de Borja A1 Palomar Pérez, Óscar A1 Rubio Sola, Jose Antonio A1 Sonmez, Nehir A1 Unsal, Osman Sabri A1 Valero Cortés, Mateo PB Institute of Electrical and Electronics Engineers (IEEE) YR 2022 K1 Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors K1 Microprocessors -- Design and construction K1 RISC-V K1 Vector processor K1 Analogue-digital conversion K1 CMOS integrated circuits K1 Logic design K1 Microprocessor chips K1 Phase locked loops K1 Reduced instruction set computing K1 Vector processor systems K1 Microprocessadors -- Disseny i construcció JF https://ieeexplore.ieee.org/document/9970128 LK http://hdl.handle.net/2117/382730 DO http://hdl.handle.net/2117/382730 SF ELIB - SuUB Bremen
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