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A Formalization of a Hierarchical Model for RISC Processors:

, In: Informatik aktuell; Europäischer Informatik Kongreß Architektur von Rechensystemen Euro-ARCH '93,
Tahar, Sofiène ; Kumar, Ramayya - p. 591-602 , 1993
Link: https://doi.org/10.1007/978-3-642-78565-8_47